AVM16: 16 channel VME 12 bit x 160 MHz ADC with features extraction

W-Ie-Ne-R presents its new 16 channel VME flash ADC equipped with 5 FPGAs for data preprocessing. The feature extraction FPGA modules allow to compute pulse integrals (also for overlapping pulses), measure and subtract pedestals, extrapolate pulse arrival times with 1.5 ns resolution, extract maxima and minima of the signal and disentangle pile up events in real time. A VXS version will soon be available.

Main features

• Bus standards                          VME/VME64, VME64x, VXS (VXS version)
• No. of channels                       16
• Input standard                        LEMO
• Sampling speed                       160 MHz
• Input voltage range                 +/- 1.000 V
• Bandwidth                               10 Hz..100 MHz (DC, full bandwidth option)

                                                             200 kHz..user limited (AC, limited bandwidth)

• Resolution                               12 bit or +/- 11 bit. Baseline setup.  
• Noise                                       0.8 LSB (RMS)
• Buffer length                           1024 samples (6.4 us). 4 buffers for 16 channe1s
• Synchronization                       External front panel connector ECL/PECL/LVDS

                                                              Dedicated VME pins

• Clock                                        Internal clock 160 MHz

                                                             External front panel connector ECL/PECL/LVDS

                                                             Dedicated VME pins

• Trigger options                        External front panel connector ECL/PECL/LVDS

                                                             Internal self-triggering mode

• Integration time window         Relative to trigger time or to pulse arrival time
• Time resolution                        1.6 ns (interpolated signal t0)
• Feature extraction                  Amplitude, Integral, Time of arrival, Multiple pulses (times, minima, maxima, partial   charges)
• Zero-suppression                   
• Thresholds                              Amplitude threshold common for all channels

                                                             Integral threshold individual for every channel

• Readout mode                         Limited verbosity (only charge and time for the main pulse)

                                                             Extended verbosity (full set of extracted parameters)

                                                             Raw data mode (plus extracted parameters)

• Self-Test                                  Internal pulse generator with programmable amplitude
• Configuration                          Remote via VME, local via JTAG connector
• Addressing space                    256 locations (0..FF)
• Base address                          00FF8000-00FFBF00  (32 locations)
• Addressing mode                    A24/D16, A24/D32, A32/D16, A32/D32, AD64, BLT, MBLT
• Power requirements               VME/VME64         +5V/ 4A,

                                                            VME64x/VXS        +5V / 2A, +3.3V/2A